agilent hmmc-3124 dc-12 ghz packaged high efficiency divide-by-4 prescaler 1gc1-8207-tr1-7" diameter reel/500 each 1gc1-8207-blk-bubble strip/10 each data sheet features ? wide frequency range: 0.2-12 ghz ? high input power sensitivity: on-chip pre- and post-amps -15 to +10 dbm (1-8 ghz) -10 to +8 dbm (8-10 ghz) -5 to +2 dbm (10-12 ghz) ? p out : 0 dbm (0.5 v pCp ) ? low phase noise: -153 dbc/hz @ 100 khz offset ? (+) or (-) single supply bias operation ? wide bias supply range: 4.5 to 6.5 volt operating range ? differential i/0 with on-chip 50 ? matching description the hmmc-3124 is a packaged gaas hbt mmic prescaler which offers dc to 12 ghz frequency translation for use in communications and ew systems incorporating high-fr equency pll oscillator circuits and si gnal-path down conversion applications. the prescaler provides a large input power sensitivity window and low phase noise. package type: 8-lead soic plastic package dimensions: 4.9 x 3.9 mm typ. package thickness: 1.55 mm typ. lead pitch: 1.25 mm nom. lead width: 0.42 mm nom. absolute maximum ratings 1 (@ t a = 25c, unless otherwise indicated) symbol parameters/conditions min. max. units v cc bias supply voltage +7 volts v ee bias supply voltage -7 volts v cc - v ee bias supply delta 0 +7 volts v logic logic threshold voltage v cc -1.5 v cc -1.2 volts p in(cw) cw rf input power +10 dbm v rfin dc input voltage (@ rf in or rf in ports) v cc 0.5 volts t bs 2 backside operating temperature -40 +85 c t st storage temperature -65 +165 c t max maximum assembly temperature 310 c (60 s max.) notes 1. operation in excess of any parameter limit (except t bs ) may cause permanent damage to the device. 2. mttf > 1 x 10 6 hours @ t bs 85c. operation in excess of maximum operating temperature (t bs ) will degrade mttf.
2 symbol parameters/conditions min. typ. max. units v cc C v ee operating bias supply difference 1 4.5 5.0 6.5 volts |i cc | or |i ee | bias supply current 34 40 46 ma v rfin(q) quiescent dc voltage appearing at all rf ports v cc volts v rfout(q) v logic nominal ecl logic level (v logic contact self-bias voltage, generated on-chip) v cc -1.45 v cc -1.32 v cc -1.25 volts notes 1. prescaler will operate over full speci? ed supply voltage range, v cc or v ee not to exceed limits speci? ed in absolute maximum ratings section. dc speci? cations/physical properties (t a = 25c, v cc C v ee = 5.0 volts, unless otherwise listed) symbol parameters/conditions min. typ. max. units ? in(max) maximum input frequency of operation 12 14 ghz ? in(min) minimum input frequency of operation 1 0.2 0.5 ghz (p in = -10 dbm) ? self-osc. output self-oscillation frequency 2 3.4 ghz p in @ dc, (square-wave input) -15 > -25 +10 dbm @ ? in = 500 mhz, (sine-wave input) -15 > -20 +10 dbm ? in = 1 to 8 ghz -15 > -20 +10 dbm ? in = 8 to 10 ghz -10 > -15 +5 dbm ? in = 10 to 12 ghz -5 > -10 +1 dbm rl small-signal input/output return loss (@ ? in < 10 ghz) 15 db s 12 small-signal reverse isolation (@ ? in < 10 ghz) 30 db n ssb phase noise (@ p in = 0 dbm, 100 khz offset from a -153 dbc/hz ? out = 1.2 ghz carrier) jitter input signal time variation @ zero-crossing 1 ps (? in = 10 ghz, p in = -10 dbm) t r or t f output transition time (10% to 90% rise/fall time) 70 ps notes 1. for sine-wave input signal. prescaler will operate down to dc for square-wave input signal. minimum divide frequency limite d by input slew-rate. 2. prescaler may exhibit this output signal under bias in the absence of an rf input signal. this condition may be eliminated by use of the input dc offset technique described on page 4. rf speci? cations (t a = 25c, z 0 = 50 ?, v cc C v ee = 5.0 volts)
3 symbol parameters/conditions min. typ. max. units p out 3 @ ? out < 1 ghz -2 0 dbm @ ? out = 2.5 ghz -3.5 -1.5 dbm @ ? out = 3.0 ghz -4.5 -2.5 dbm |v out(pCp) | 4 @ ? out < 1 ghz 0.5 volts @ ? out = 2.5 ghz 0.42 volts @ ? out = 3.0 ghz 0.37 volts p spitback ? out power level appearing at rf in or rf in -50 dbm (@ ? in 10 ghz, unused rf out or rf out unterminated ) ? out power level appearing at rf in or rf in -55 dbm (@ ? in = 10 ghz, both rf out & rf out terminated ) p feedthru power level of ? in appearing at rf out or rf out -30 dbc (@ ? in = 12 ghz, p in = 0 dbm, referred to p in (? in )) h 2 second harmonic distortion output level (@ ? out = 3.0 ghz, referred to p out (? out )) -25 dbc notes 3. fundamental of output square wave's fourier series. 4. square wave amplitude calculated from p out . rf speci? cations (continued) (t a = 25c, z 0 = 50 ?, v cc C v ee = 5.0 volts) applications the hmmc-3124 is designed for use in high frequency communications, micro- wave instrumentation, and ew radar systems where low phase-noise pll control circuitry or broad-band frequency translation is required. operation the device is designed to operate when driven with either a single-ended or differential sinusoidal input signal over a 200 mhz to 12 ghz bandwidth. below 200 mhz the pr escaler input is slew-rate limited, requiring fast rising and falling edge speeds to properly divide. the device will operate at frequencies down to dc when driven with a square-wave. due to the presence of an off-chip rf-bypass capacitor inside the package (connected to the v cc contact on the device), and the unique design of the device itself, the component may be biased from either a single positive or single negative supply bias. the backside of the package is not dc con- nected to any dc bias point on the device. for positive supply operation, v cc pins are nominally biased at any voltage in the +4.5 to +6.5 volt range with pin 8 (v ee ) grounded. for negative bias op- eration v cc pins are typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to pin 8 (v ee ). ac-coupling and dc-blocking all rf ports are dc connected on-chip to the v cc contact through on-chip 50 ? resistors. under any bias conditions where v cc is not dc grounded the rf ports should be ac coupled via series capacitors m ounted on the pc board at each rf po rt. only under bias conditions where v cc is dc grounded (as is typi- cal for negative bias supply operation) may the rf ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. in the latter case the package heat sink may be ? oated and bias applied as the difference between v cc and v ee .
4 input dc offset if an rf signal with suf? cient signal to noise ratio is present at the rf input lead, the prescaler will operate and provide a divided output equal the input frequency divided by the divide modulus. under certain "ideal" condi- tions where the input is well matched at the right input frequency, the com- ponent may "self-oscillate", especially under small signal input powers or with only noise present at the input. this self-oscillation will produce a undesired output signal also known as a false trigger. to prevent false triggers or self-oscillation conditions, apply a 20 to 100 mv dc offset voltage between the rf in and rf in ports. this prevents noise or spurious low level signals from triggering the divider. adding a 10 k? resistor between the unused rf input to a contact point at the v ee potential will result in an offset of 25 mv between the rf inputs. note ho wever, that the input sensitivity will be r educed slightly due to the presence of this offset. assembly notes i ndependent of the bias applied to the package, the backside of the package should always be connected to both a good rf ground plane and a good thermal heat sinking region on the pc board to optimize performance. for single-ended output operation the unused rf output lead should be ter- minated into 50 ? to a contact point at the v cc potential or to rf ground through a dc blocking capacitor. a minimum rf and thermal pc board contact area equal to or greater than 2.67 1.65 mm (0.105" 0.065") with eight 0.020" diameter plated-wall thermal vias is recommended. mmic esd precautions, handling considerations, die attach and bond- ing methods are critical factors in suc- cessful gaas mmic performance and reliability. agilent application note #54, gaas mmic esd, die attach and bonding guidelines provides basic information on these subjects. moisture sensitivity classi? cation: class 1, per jesd22-a112-a. additional references: pn #18, "hbt prescaler evaluation board." figure 1. simpli? ed schematic
5 figure 2. package and dimensions figure 3. assembly diagram (single-supply, positive-bias con? guration shown) symbol min. max. a 1.35 1.75 a1 0.0 .25 b 0.33 0.51 c 0.19 .025 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc 1.27 bsc h 5.80 6.20 l 0.40 1.27 a 0 8 notes : ? all dimensions in millimeters. ? refer to jedec outline ms-012 for additional tolerances. ? exposed heat slug area on package bottom = 2.67 x 1.65. ? exposed heat sink on package bottom must be soldered to pcb rf ground plane.
6 figure 4. typical input sensitivity window figure 5. typical supply current & v logic vs. supply voltage figure 6. typical phase noise performance figure 7. typical output power vs. output frequency, ? out (ghz) figure 8. typical spitback power p(? out ) appearing at rf input port
7 device orientation notes : 1. 10 sprocket hole pitch cumulative tolerance: 0.2 mm. 2. camber not to exceed 1 mm in 100 mm. 3. material: black conductive advantek polystyrene. 4. ao and bo measured on a plane 0.3 mm above the bottom of the pocket. 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. tape dimensions and product orientation
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